1. Field of the Invention
The present invention relates in general to an organic light emitting diode (OLED) display, and more particularly to an OLED display which is able to avoid the parasitic capacitance between the cathode electrodes and scan lines or data lines, and thus the consequential resistance capacitance time delay (RC delay) is prevented.
2. Description of the Related Art
OLED display technology requires no backlighting—unlike liquid crystal display (LCD) panel, since OLED pixels are self-luminous by way of current driven or voltage driven. Additional advantages of OLED displays are exceptionally wide viewing angle and full-colour. Therefore, the OLED displays are expected to replace LCDs in most flat-panel display applications which include personal digital assistants (PDAs), cell phones, and more.
FIG. 1 is a schematic diagram showing a circuit configuration of a conventional OLED display. An OLED display 100 includes a data driver 120, a scan driver 130, a cathode electrode 108, data lines 102, power lines 104, scan lines 106, pixel areas 110, VSS 140a and 140b, metal layers 150a, 150b, 150c and 150d, and contact holes 160a, 160b, 160c and 160d. 
The data lines 102 are parallel to the power supply lines 104. And both the data lines 102 and the power lines 104 are perpendicular to the scan lines 106 to form a number of pixels, each of which possesses a pixel area 110, respectively. All the pixel areas 110 form a pixel area array 115.
The data driver 120 drives all the data lines 102 and provides the data lines with data signals. The data lines 102 then transmit the data signals to the corresponding pixels. The scan driver 130 drives all the scan lines 106 and provides the scan lines with scan signals. The scan lines 106 then transmit the scan signals to the corresponding pixels. Besides, the power supply lines 104 function as transmitting the power to the corresponding pixels. Each pixel generates different levels of brightness according to the level of voltage it receives.
The pixel area array 115 is surrounded by the metal layers 150a, 150b, 150c, and 150d, which are respectively at the upper side, right side, bottom side, and left side of the pixel area array 115. The VSS 140a and 140b are electrically coupled to the metal layers 150a, 150b, 150c, and 150d. 
The cathode electrode 108 covers the pixel area array 115 and the metal layers 150a, 150b, 150c, and 150d including the scan lines 106, the data lines 102, and the power supply lines 104. The cathode electrode 108 is electrically coupled to the metal layers 150a, 150b, 150c, and 150d through the contact holes 160a, 160b, 160c, and 160d outside of the pixel area array 115. Therefore, the cathode electrode 108 can be electrically coupled to the VSS 140a and 140b. 
In addition, there are at least two thin film transistors (TFTs), a capacitor, and an electroluminescence display device 170 for each pixel.
FIG. 2 is a cross-sectional view of the conventional OLED display in FIG. 1. Three pixels of the OLED display are shown in FIG. 2 for example. The gate of TFT 205 is formed on the transparent substrate 202 and is covered by the gate insulating layer 203. The scan lines 106 shown in FIG. 1 (not shown in FIG. 2) are formed on the transparent substrate 202 and also covered by the gate insulating layer 203. Further, the drain and source of TFT 205 are formed on the gate insulating layer 203. The drain and source of TFT 205 are covered by the interlayer insulating layer 204 which is further covered by the planarization insulating layer 206. The data lines 102 and the power supply lines 104 are disposed on the interlayer insulating layer 204 and covered by the planarization insulating layer 206. The anode electrodes 207 are formed on the surface of the planarization insulating layer 206, corresponding to each pixel. Furthermore, the sources of the TFT 205 are coupled to the anode electrode 207 and the drains of the TFT 205 are coupled to the power supply lines 104.
The stack structure of a second TFT in each pixel (not shown in FIG. 2), other than the TFT 205, is similar to the TFT 205, but it is electrically coupled to the capacitor and the drain thereof is electrically coupled to the data lines 102.
The hole transport layer 208 is formed on the anode electrode 207 and the planarization insulating layer 206, covering all pixels. The emissive layer 209 is formed on the hole transport layer 208, corresponding to each pixel. The electron transport layer 210 is formed on the emissive layer 209 and the hole transport layer 208, covering all pixels. The cathode electrode 108 is formed on the electron transport layer 210. Therefore, the anode electrodes 207, the hole transport layer 208, the emissive layer 209, the electron transport layer 210, and the cathode electrode 108 together form the electroluminescence display device 170. The holes and the electrons respectively transmitted from the hole transport layer 208 and the electron transport layer 210 meet in the emissive layer 209 so that light can be emitted from the emissive layer 209 toward outside along the direction indicated by the arrow 250, as shown in FIG. 2.
However, the image quality of the OLED display will be affected by the resistance capacitance time delay (RC delay). The RC delay is caused from the parasitic capacitance between the cathode electrode 108 and scan lines or data lines respectively. From a top view, the scan lines 106 and the data lines 102 are covered under the cathode electrode 108 of a conventional OLED display according to the overall covering cathode electrode.
FIG. 3A is a cross-sectional view of a part of FIG. 1 around the data line. The circuit configuration of the OLED display 100 is a multi-layer stack structure whose arrangement from bottom to top is the transparent substrate 202, the gate insulating layer 203, the interlayer insulating layer 204, the data lines 102, the planarization insulating layer 206, the hole transport layer 208, the electron transport layer 210, and the cathode electrode 108.
The parasitic capacitance between the cathode electrode 108 and the data lines 102 is formed since the cathode electrode 108 is above the data lines 102 to affect image quality and cause the resistance capacitance time delay. Furthermore, it will result in the data signals delay of the data lines 102.
FIG. 3B is a cross-sectional view of a part of FIG. 1 around the scan line. The multi-layer stack structure of the OLED display 100 arranged from bottom to top is the transparent substrate 202, the scan lines 106, the gate insulating layer 203, the interlayer insulating layer 204, the planarization insulating layer 206, the hole transport layer 208, the electron transport layer 210, and the cathode electrode 108.
Also, the parasitic capacitance between the cathode electrode 108 and the scan lines 106 is formed since the cathode electrode 108 is above the scan lines 106 to cause the resistance capacitance time delay. Furthermore, it will result in the scan signals delay of the scan lines 106.
As the size of OLED display 100 extends, the amount of the parasitic capacitance respectively forming between the cathode electrode 108 and the data lines 102 or the scan lines 106 grows and it will result in worse RC delay. The problems such as cross talk and inefficiency of the power supply affect the OLED display 100 hugely because the data signals delay and the scan signals delay are both resulted from the RC delay respectively. Besides, owing to the capacitive losses power is in proportion to the parasitic capacitance, the capacitive losses power of the OLED display 100 will increase relatively with the increasing parasitic capacitance when the OLED display size extends.